HMT451U6MFR8C Datasheet, PDF (35/55 Pages) Hynix Semiconductor – DDR3 SDRAM Unbuffered DIMMs Based on 4Gb M-Die

DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read command to first
data
t_AA
ACT to internal read or write
delay time
t_RCD
PRE command period
t_RP
ACT to ACT or REF command
period
t_RC
DDR3-1600K
11-11-11
min
13.75
(13.125)^5,10
13.75
(13.125)^5,10
13.75
(13.125)^5,10
48.75
(48.125)^5,10
max
20
—
—
—
ACT to PRE command period t_RAS
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 7
CL = 8
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 9
CWL = 7
t_CK(AVG)
CWL = 8
t_CK(AVG)
CWL = 5, 6
t_CK(AVG)
CL = 10
CWL = 7
t_CK(AVG)
CWL = 8
t_CK(AVG)
CL = 11
CWL = 5, 6,7
CWL = 8
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
35
9 * tREFI
2.5
3.3
Reserved
Reserved
Reserved
1.875
< 2.5
(Optional)^5,10
Reserved
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
Reserved
1.5
<1.875
(Optional)^5,10
Reserved
Reserved
1.5
<1.875
Reserved
Reserved
1.25
<1.5
6, (7), 8, (9), 10, 11
5, 6, 7, 8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n_CK
n_CK
Note
1, 2, 3, 8
1, 2, 3, 4, 8
4
4
1, 2, 3, 4, 8
1, 2, 3, 4, 8
4
4
1, 2, 3, 8
1, 2, 3, 4, 8
1, 2, 3, 4
4
1, 2, 3, 4, 8
1, 2, 3, 4
4
1, 2, 3, 8
1,2,3,4
4
1, 2, 3
Rev. 1.1 / Jul. 2013
35