HMT451U6MFR8C Datasheet, PDF (33/55 Pages) Hynix Semiconductor – DDR3 SDRAM Unbuffered DIMMs Based on 4Gb M-Die

DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read command to
first data
t_AA
ACT to internal read or
write delay time
t_RCD
DDR3-1066F
7-7-7
min
13.125
max
20
13.125
—
PRE command period
t_RP
13.125
—
ACT to ACT or REF
command period
t_RC
ACT to PRE command
period
t_RAS
CL = 6
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 7
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 8
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
50.625
—
37.5
2.5
1.875
1.875
Reserved
Reserved
Reserved
6, 7, 8
5, 6
9 * tREFI
3.3
< 2.5
< 2.5
Unit
Note
ns
ns
ns
ns
ns
ns
1, 2, 3, 6
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3
n_CK
n_CK
Rev. 1.1 / Jul. 2013
33