HMT451U6MFR8C Datasheet, PDF (36/55 Pages) Hynix Semiconductor – DDR3 SDRAM Unbuffered DIMMs Based on 4Gb M-Die

DDR3-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3-1866M
CL - nRCD - nRP
Parameter
Symbol
Internal read command
to first data
t_AA
ACT to internal read or
write delay time
t_RCD
PRE command period
t_RP
ACT to PRE command
period
ACT to ACT or PRE
command period
CWL = 5
CL = 6 CWL = 6
CWL = 7,8,9
CWL = 5
t_RAS
t_RC
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 7
CWL = 6
t_CK(AVG)
CL = 8
CWL = 7,8,9
CWL = 5
CWL = 6
CWL = 7
CWL = 8,9
CWL = 5, 6
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 9
CL = 10
CWL = 7
CWL = 8
CWL = 9
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 5,6,7
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 11 CWL = 8
t_CK(AVG)
CWL = 9
t_CK(AVG)
CL
=
12
CWL = 5,6,7,8
CWL = 9
t_CK(AVG)
t_CK(AVG)
CL
=
13
CWL = 5,6,7,8
CWL = 9
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
min
13.91
(13.125)^5,11
13.91
(13.125)^5,11
13.91
(13.125)^5,11
34
13-13-13
max
20
—
—
9 * tREFI
47.91
(47.125)^5,11
-
2.5
3.3
Reserved
Reserved
Reserved
1.875
< 2.5
(Optinal)
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
Reserved
1.5
<1.875
(Optinal)
Reserved
Reserved
Reserved
1.5
<1.875
Reserved
Reserved
1.25
<1.5
(Optinal)
Reserved
Reserved
Reserved
Reserved
1.07
<1.25
6, 7, 8, 9, 10, 11, 13
5, 6, 7, 8, 9
Rev. 1.1 / Jul. 2013
Unit
Note
ns
ns
ns
ns
ns
ns
1, 2, 3, 9
ns
1, 2, 3, 4, 9
ns
4
ns
4
ns
1, 2, 3, 4, 9
ns
4
ns
4
ns
1, 2, 3, 9
ns
1, 2, 3, 4, 9
ns
4
ns
4
ns
1, 2, 3, 4, 9
ns
1, 2, 3, 4, 9
ns
4
ns
4
ns
1, 2, 3, 9
ns
1, 2, 3, 4, 9
ns
4
ns
1, 2, 3, 4, 9
ns
1, 2, 3, 4
ns
4
ns
1,2,3,4
ns
4
ns
1, 2, 3
n_CK
n_CK
36