GM71V18163C Datasheet, PDF (5/11 Pages) Hynix Semiconductor – 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM

GM71V18163C
GM71VS18163CL
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C)
Symbol
Parameter
Min Max Unit Note
CI1
Input Capacitance (Address)
-
5
pF
1
CI2
Input Capacitance (Clocks)
-
7
pF
1
CI/O
Output Capacitance (Data-In/Out)
-
7
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. UCAS and LCAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Note 1, 2, 18, 19, 20)
Test Conditions
Input rise and fall times : 2 ns
Output timing reference levels : 0.8V, 2.0V
Input levels : VIL = 0V, VIH = 3V
Input timing reference levels : 0.8V, 2.0V
Output load : 1TTL gate + CL (100 pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
Note
tRC
Random Read or Write Cycle Time
84 - 104 - 124 -
ns
tRP
RAS Precharge Time
30 - 40 - 50 -
ns
tCP
CAS Precharge Time
8 - 10 - 13 -
ns
tRAS RAS Pulse Width
tCAS CAS Pulse Width
tASR Row Address Set up Time
tRAH Row Address Hold Time
tASC Column Address Set-up Time
tCAH Column Address Hold Time
tRCD RAS to CAS Delay Time
tRAD RAS to Column Address Delay Time
tRSH RAS Hold Time
tCSH CAS Hold Time
tCRP CAS to RAS Precharge Time
tODD OE to DIN Delay Time
tDZO OE Delay Time from DIN
tDZC CAS Delay Time from DIN
tT
Transition Time (Rise and Fall)
50 10,000 60 10,000 70 10,000 ns
8 10,000 10 10,000 13 10,000 ns
0-
0-
0-
ns
8 - 10 - 10 -
ns
0-
0-
0-
ns
21
8 - 10 - 13 -
ns
21
12 37 14 45 14 52
ns
3
10 25 12 30 12 35
ns
4
10 - 13 - 13 -
ns
35 - 40 - 45 -
ns
23
5-
5-
5-
ns
22
13 - 15 - 18 -
ns
5
0-
0-
0-
ns
6
0-
0-
0-
ns
6
2 50
2 50
2 50
ns
7
Rev 0.1 / Apr’01