GM71V18163C Datasheet, PDF (3/11 Pages) Hynix Semiconductor – 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM

GM71V18163C
GM71VS18163CL
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
Parameter
Min Typ Max Unit
VCC
Supply Voltage
3.0
3.3
3.6
V
VIH
Input High Voltage
2.0
-
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
-
0.8
V
Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.
Truth Table
RAS LCAS UCAS WE OE Output
Operation
Notes
H
D
D
D
D
Open
Standby
1,3
L
L
H
H
L
Valid
Lower byte
L
H
L
H
L
Valid
Upper byte
Read cycle
1,3
L
L
L
H
L
Valid
Word
L
L
H
L
D
Open
Lower byte
L
H
L
L
D
Open
Upper byte Early write cycle 1,2,3
L
L
L
L
L
H
L
L
L
L
L
H
L
L
H to L
H
H to L
L
H to L
L
L
L
D
Open
Word
H
L
H
Undefined Lower byte
L
L
H
Undefined _{Upper byte} ^{Delayed Write} _1,2,3
cycle
L
L
H
Undefined
Word
H
H to L L to H
Valid
Lower byte
L
H to L L to H
Valid
Upper byte
Read-modify
-write cycle
1,3
L
H to L L to H
Valid
Word
L
D
D
H
D
D
L
D
D
Open
Open
Open
Word
Word
Word
CBR Refresh
or
Self Refresh
1,3
(L-series)
L
H
H
D
D
Open
L
L
L
H
H
Open
Word
RAS-only
Refresh cycle
1,3
Read cycle
(Output disabled)
1,3
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2. tWCS >= 0ns Early write cycle
tWCS <= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr’01