HY5PS561621BLFPE3 Datasheet, PDF (31/34 Pages) Hynix Semiconductor – 256Mb DDR2 SDRAM

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1HY5PS561621B(L)FP
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to the derating
value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_REF(dc) and the first crossing
of V_IH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V_REF(dc) and
the first crossing of V_IL(ac)max. If the actual signal is always earlier than the nominal slew rate for line between shaded ‘V_REF(dc) to
ac region’, use nominal slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘V_REF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for der-
ating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first cross-
ing of V_REF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V_REF(dc). If the
actual signal signal is always later than the nominal slew rate line between shaded ‘dc to V_REF(dc) region’, use nominal slew rate for
derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to V_REF(dc)
region’, the slew rate of a tangent line to the actual signal from the dc level to V_REF(dc) level is used for derating value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached V_IH/IL(ac) at the time of
the rising clock transition) a valid input signal is still required to complete the transition and reach V_IH/IL(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH are = 50%
of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( t
JIT(crosstalk)) into the clock traces.
12. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both
of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as
well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle.
14. DAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application
clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.
tDAL = 4 + (15ns/3.75ns) clocks = 4+(4) clocks = 8 clocks.
15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock
frequency change during precharge power-down, a specific procedure is required as described in section 2.9.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
17. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are referenced to a
specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving (tLZ). Below figure
Rev. 0.2 / Apr. 2008
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