HY5PS561621BLFPE3 Datasheet, PDF (23/34 Pages) Hynix Semiconductor – 256Mb DDR2 SDRAM

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1HY5PS561621B(L)FP
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This
distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled
via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper
operation.
DQS/
DQS
DQ
DM
DQS
t_DQSH
t_DQSL
DQS
t_WPRE
V_IH(ac)
D
V_IL(ac)
t_DS
DMin
D
V_IH(ac)t^DS
DMin
V_IL(ac)
V_IH(dc)
D
V_IL(dc)
t_DH
DMin
t_WPST
D
t_{DH VIH(dc)}
DMin
V_IL(dc)
Figure -- Data input (write) timing
CK
CK/CK
CK
DQS/DQS
DQ
t_CH
t_CL
DQS
DQS
t_RPRE
t_DQSQmax
Q
t_QH
Q
Q
t_DQSQmax
Figure -- Data output (read) timing
t_RPST
Q
t_QH
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
Rev. 0.2 / Apr. 2008
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