HYMP512U648 Datasheet, PDF(3/24 Page) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.

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HYMP512U648 Datasheet, PDF (3/24 Pages) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.

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1240pin DDR2 SDRAM Unbuffered DIMMs

Symbol

Type

Polarity

Pin Description

During a Bank Activate command cycle, Address input difines the row address(RA0~RA15)

A[9:0], A10/AP,

A[13:11]

DQ[63:0],

CB[7:0]

DM[8:0]

VDD,VSS

DQS[8:0],

DQS[8:0]

SA[2:0]

SDA

SCL

VDDSPD

SSTL

During a Read or Write command cycle, Address input defines the column address when

sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to

the column address, AP is used to invoke autoprecharge operation at the end of the burst

read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank

to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command

cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP

is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low,

then BA0-BAn are used to define which bank to precharge.

SSTL

Data and Check Bit Input/Output pins.

SSTL

DM is an input mask signal for write data. Input data is masked when DM is sampled High

Active High coincident with that input data during a write access. DM is sampled on both edges of

DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.

Supply

Power and ground for the DDR2 SDRAM input buffers, and core logic.

VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules.

Differential Data strobe for input and output data. For Rawcards using x16 organized DRAMs, DQ0~7

SSTL

crossing connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of the DRAM

These signals are tied at the system planar to either VSS or VDD to configure the serial SPD

EEPROM.

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister

must be connected to VDD to act as a pull up.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-

nected from SCL to VDD to act as a pull up on the system board.

Supply

Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.

EEPROM supply is operable from 1.7V to 3.6V.

PIN CONFIGURATION

Front Side

1 pin

64 pin 65 pin

120 pin

121 pin

Back Side

184 pin 185 pin

240 pin

Rev. 1.0 / Apr. 2005

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