HYMP512U648 Datasheet, PDF (2/24 Pages) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.

1240pin DDR2 SDRAM Unbuffered DIMMs
SPEED GRADE & KEY PARAMETERS
Speed @CL3
Speed @CL4
Speed @CL5
CL-tRCD-tRP
E3 (DDR2-400)
400
400
-
3-3-3
C4 (DDR2-533)
400
533
-
4-4-4
Unit
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density Organization Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
256MB 32M x 64
1
32Mb x 16
4
13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
512MB 64M x 64
1
64Mb x 8
8
13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
512MB 64M x 72
1
64Mb x 8
9
13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
1GB
128M x 64
2
64Mb x 8
16
14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
1GB
128M x 72
2
64Mb x 8
18
14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
Input/Output Functional Description
Symbol
Type Polarity
Pin Description
CK[2:0], CK[2:0] SSTL
CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sam-
Differential
pled on the crossing of positive edge of CK and negative edge of /CK. Output(read) data is
Crossing
reference to the crossing of CK and /CK (Both directions of crossing)
CKE[1:0]
SSTL
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
Active High By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
S[1:0]
SSTL
Enables the associated DDR2 SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands are
Active Low
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1
RAS, CAS, WE SSTL Active Low /RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
ODT[1:0]
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SSTL Active High
SDRAM mode register.
Vref
Supply
Reference voltage for SSTL18 inputs
V_DDQ
Supply
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity.
For all current DDR2 unbuffered DIMM designs, V_DDQ shares the same power plane as V_DD
pins.
BA[1:0]
SSTL
-
Selects which DDR2 SDRAM internal bank of four is activated.
Rev. 1.0 / Apr. 2005
2