HYMP512U648 Datasheet, PDF (18/24 Pages) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.

1240pin DDR2 SDRAM Unbuffered DIMMs
IDD MEASUREMENT CONDITIONS
Symbol
Conditions
IDD0
Operating one bank active-precharge current; ^tCK = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRAS} = ^{tRASmin(IDD);CKE}
is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are
SWITCHING
IDD1
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; ^tCK =
tCK(IDD), tRC ₌ tRC _(IDD), tRAS ₌ tRASmin(IDD), tRCD ₌ tRCD(IDD) _{; CKE is HIGH, CS is HIGH between}
valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
IDD2P
Precharge power-down current ; All banks idle ; tCK = ^tCK(IDD) ; CKE is LOW ; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
IDD2Q
Precharge quiet standby current;All banks idle; ^tCK = ^tCK(IDD);CKE is HIGH, CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2N
Precharge standby current; All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD3P
Active power-down current; All banks open; ^tCK = ^tCK(IDD); CKE is LOW; _{Fast PDN Exit MRS(12) = 0}
Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Slow PDN Exit MRS(12) = 1
IDD3N
Active standby current; All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} =tRP(IDD); CKE is HIGH,
CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; ^tCK =
tCK(IDD), tRAS ₌ tRASmax(IDD), tRP ₌ tRP(IDD); _{CKE is HIGH, CS is HIGH between valid commands;}
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= 0; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
IDD5B
Burst refresh current; ^tCK = ^tCK(IDD); Refresh command at every ^tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6
current values are guaranted up to Tcase of 85℃ max.
Normal
Low Power
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =
tRCD(IDD)-1*tCK(IDD); tCK ₌ tCK(IDD), tRC ₌ tRC(IDD), tRRD ₌ tRRD(IDD), tRCD _{= 1*tCK(IDD); CKE is}
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern
is same as IDD4R; - Refer to the following page for detailed timing conditions
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with
all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for
address and control sig nals, and inputs changing between HIGH and LOW every other
data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 1.0 / Apr. 2005
18