HYMP512U648 Datasheet, PDF (1/24 Pages) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.

240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine
Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based DDR2 Unbuffered
DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is
suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchrnous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
• All inputs and outputs are compatible with SSTL_1.8
interface
• 4 Bank architecture
• Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA(64Mx8), 84ball
FBGA(32Mx16)
• 133.35 x 30.00 mm form factor
• Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name
HYMP532U646-E3/C4
HYMP564U648-E3/C4
HYMP564U728-E3/C4
HYMP512U648-E3/C4
HYMP512U728-E3/C4
HYMP532U64P6-E3/C4
HYMP564U64P8-E3/C4
HYMP564U72P8-E3/C4
HYMP512U64P8-E3/C4
HYMP512U72P8-E3/C4
Density
256MB
512MB
512MB
1GB
1GB
256MB
512MB
512MB
1GB
1GB
Organization
32Mx64
64Mx64
64Mx72
128Mx64
128Mx72
32Mx64
64Mx64
64Mx72
128Mx64
128Mx72
# of
DRAMs
4
8
9
16
18
4
8
9
16
18
# of
ranks
1
1
1
2
2
1
1
1
2
2
Materials
Leaded
Leaded
Leaded
Leaded
Leaded
Lead free
Lead free
Lead free
Lead free
Lead free
ECC
None
None
ECC
None
ECC
None
None
ECC
None
ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Apr. 2005
1