HY5PS561621BLFPE3I Datasheet, PDF (27/34 Pages) Hynix Semiconductor – 256Mb DDR2 SDRAM

Fig. -b Illustration of tangent line for tIS,tDS
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1HY5PS561621B(L)FP-xI
CK, DQS
CK, DQS
V_DDQ
V_IH(ac)min
t_IS,
t_IH,
t_DS
t_DH
nominal
line
t_IS,
t_IH,
t_DS
t_DH
V_IH(dc)min
tangent
line
V_REF(dc)
V_IL(dc)max
Tangent
line
V_IL(ac)max
Nomial
line
Vss
Delta TR
V_REF to ac
region
Delta TF
Setup Slew Rate
Rising Signal
= ^{Tangent line[VIH(ac)min-VREF(dc)]}
Delta TR
Setup Slew Rate
Falling Signal
=
Tangent
line[VREF(dc)-V_IL(ac)max]
Delta TF
Rev. 0.2 / Apr. 2008
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