HY5PS561621BLFPE3I Datasheet, PDF (18/34 Pages) Hynix Semiconductor – 256Mb DDR2 SDRAM

1
1HY5PS561621B(L)FP-xI
Timing Parameters by Speed Grade
(Refer to notes for information related to this table at the following pages of this table)
Parameter
Symbol
DDR2-400
min
max
DDR2-533
min
max
DQ output access time from CK/CK
tAC
-600
+600
-500
+500
DQS output access time from CK/CK
tDQSCK
-500
+500
-450
+450
CK high-level width
tCH
0.45
0.55
0.45
0.55
CK low-level width
tCL
0.45
0.55
0.45
0.55
CK half period
tHP
min(tCL,tCH)
-
min(tCL,tCH)
-
Clock cycle time, CL=x
tCK
5000
8000
3750
8000
DQ and DM input setup time(differential strobe) tDS(base)
150
-
100
-
DQ and DM input hold time(differential strobe)
tDH(base)
275
-
225
-
DQ and DM input setup time(single ended strobe) tDS
25
-
-25
-
DQ and DM input hold time(single ended strobe) tDH
25
-
-25
-
Control & Address input pulse width for each input tIPW
0.6
-
0.6
-
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
DQS-DQ skew for DQS and associated DQ signals tDQSQ
-
350
-
300
DQ hold skew factor
tQHS
-
450
-
400
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
First DQS latching transition to associated clock
edge
tDQSS
-0.25
+ 0.25
-0.25
+ 0.25
DQS input high pulse width
tDQSH
0.35
-
0.35
-
DQS input low pulse width
tDQSL
0.35
-
0.35
-
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
Mode register set command cycle time
tMRD
2
-
2
-
Write postamble
tWPST
0.4
0.6
0.4
0.6
Write preamble
tWPRE
0.35
-
0.35
-
Address and control input setup time
tIS(base)
350
-
250
-
Address and control input hold time
tIH(base)
475
-
375
-
Read preamble
tRPRE
0.9
1.1
0.9
1.1
Read postamble
tRPST
0.4
0.6
0.4
0.6
Active to active command period
tRRD
7.5
-
7.5
-
Four Activate Window
tFAW
37.5
-
37.5
-
CAS to CAS command delay
tCCD
2
2
Write recovery time
tWR
15
-
15
-
Auto precharge write recovery + precharge time tDAL
WR+tRP
-
WR+tRP
-
Internal write to read command delay
tWTR
10
-
7.5
-
Internal read to precharge command delay
tRTP
7.5
7.5
Unit Note
ps
ps
tCK
tCK
ps
11,12
ps
15
ps 6,7,8,20
ps 6,7,8,21
ps 6,7,8,20
ps 6,7,8,21
tCK
tCK
ps
18
ps
18
ps
18
ps
13
ps
12
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
10
tCK
ps 5,7,9,23
ps 5,7,9,23
tCK
tCK
ns
4
ns
tCK
ns
tCK
14
ns
24
ns
3
Rev. 0.2 / Apr. 2008
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