HY5DU283222AQP Datasheet, PDF (23/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

FUNCTION DESCRIPTION
HY5DU283222AQP
Burst Read and Burst Write
Burst Read and Burst Write commands are initiated as listed in Fig.1. Before the Burst Read command, the bank must
be activated earlier. After /RAS to /CAS delay (tRCD), read operation starts. DDR SDRAM has been implemented with
Data Strobe signal (DQS) which toggles high and low during burst with the same frequency as clock (CLK, /CLK). After
CAS Latency (CL) which is defined as the interval between command clock and the first rising edge of the DQS, read
data is launched onto data pin (DQ) with reference to DQS signal edge. Burst Write command in another bank can be
given with having activated that bank where /RAS to /RAS delay (tRRD) is satisfied. Write data is also referenced and
aligned to the DQS signal sent from the memory controller. Since all read operation bursts data out at both the rising
and the falling of the DQS, double data bandwidth can be achieved, also for write data.
Fig.1. Burst Read and Burst Write
/CLK
CLK
CKE
/CS
RA, CA
AP
BA
tRRD
Row_A
tRCD
CL
Col_A
Row_B
Row_A
No PCG
Row_B
Bank 0
Bank 0
Bank 1
Col_B
AutoPCG
Bank 1
/RAS
/CAS
/WE
DM
Activate
Bank 0
Read
Bank 0
Activate
Bank 1
Write Bank 1
w/ Autopcg
DQS
DQ
Burst length =4, CAS latency =2
A0 A1 A2 A3
Bank 0 Data-out
B0 B1 B2 B3
Bank 1 Data-in
Rev. 0.1 / Jan. 2005
23