HY5DU283222AQP Datasheet, PDF (22/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQP
EXTENDED MODE REGISTER SET (EMRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of RAS, CAS, CS, WE and BA0. This command can be issued only when all banks are in idle state and CKE must
be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the
data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is deter-
mined, the information will be held until resetted by another MRS command.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
RFU*
DS
RFU*
DS DLL
BA0 MRS Type
0
MRS
1
EMRS
A0 DLL enable
0
Enable
1
Diable
A2 A6 A1 Output Driver Impedance Control
000
RFU*
001
Half (60%)
010
RFU*
011
Weak (40%)
100
RFU*
101
Semi Half (50%)
110
RFU*
111
Semi Weak (30%)
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
Rev. 0.1 / Jan. 2005
22