HYMP112P72CP8L-C4 Datasheet, PDF (22/27 Pages) Hynix Semiconductor – 240pin DDR2 VLP Registered DIMMs

1240pin DDR2 VLP Registered DIMMs
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Parameter
Symbol
DDR2-667
min
max
DDR2-800
min
max
Unit Note
CAS to CAS command delay
tCCD
2
2
tCK
Write recovery time
tWR
15
-
15
-
ns
Auto precharge write recovery + precharge time tDAL
WR+tRP
-
WR+tRP
-
tCK
Internal write to read command delay
tWTR
7.5
-
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
7.5
ns
tRFC +
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
10
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
Exit precharge power down to any non-read
tXP
command
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
2
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
7 - AL
8 - AL
tCK
CKE minimum pulse width
(high and low pulse width)
tCKE
3
3
tCK
ODT turn-on delay
tAOND
2
2
2
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)
+0.7
tAC(min)
tAC(max)
+0.7
ns
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+2
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
ns
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)
+0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)
+2
2.5tCK+ tAC(min) 2.5tCK+
tAC(max)+1 +2 tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay tIS+tCK+tIH
tIS+tCK
+tIH
ns
Average periodic Refresh Interval
tREFI
-
7.8
-
7.8
us
2
tREFI
-
3.9
-
3.9
us
3
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[4,8]31CFP).
2. 0°C †
TCASE †
°C

°C ģ
TCASE
†
°C
Rev. 0.2 / May. 2008