English
Language : 

HYMP112P72CP8L-C4 Datasheet, PDF (11/27 Pages) Hynix Semiconductor – 240pin DDR2 VLP Registered DIMMs
◁
INPUT DC LOGIC LEVEL
1240pin DDR2 VLP Registered DIMMs
Parameter
Symbol
Input High Voltage
Input Low Voltage
VIH(DC)
VIL(DC)
INPUT AC LOGIC LEVEL
Min
VREF + 0.125
-0.30
Max
VDDQ + 0.3
VREF - 0.125
Unit
V
V
Notes
Parameter
AC Input logic High
AC Input logic Low
Symbol
VIH(AC)
VIL(AC)
DDR2 400/533
Min
Max
VREF + 0.250
-
-
VREF - 0.250
DDR2 667/800
Min
Max
VREF + 0.200
-
-
VREF - 0.200
Unit
V
V
Notes
AC INPUT TEST CONDITIONS
Symbol
VREF
VSWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * VDDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
VSWING(MAX)
delta TF
Falling Slew = VREF - VIL(ac) max
delta TF
delta TR
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
Rising Slew = VIH(ac)min - VREF
delta TR
Rev. 0.2 / May. 2008
< Figure : AC Input Test Signal Waveform>
 ▷