HY5PS12421BFP-E3 Datasheet, PDF (18/38 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are
IDD6
mA
FLOATING; Data bus inputs are FLOATING
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = ^{tRCD(IDD)-1*tCK(IDD); tCK} = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRRD} = ^tRRD(IDD),
tRCD _{= 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are} mA
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
Note:
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V
(exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
6. Definitions for IDD
LOW is defined as Vin £ VILAC(max)
HIGH is defined as Vin Å  VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
Rev. 0.7 / Oct. 2007
18