HY5PS12421BFP-E3 Datasheet, PDF (17/38 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
Conditions
IDD0
Operating one bank active-precharge current; ^tCK = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRAS} =
tRAS _{min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are}
SWITCHING;Data bus inputs are SWITCHING
Units
mA
IDD1
Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
= 0; ^tCK = ^{tCK(IDD), tRC} = ^tRC (IDD), ^tRAS = ^{tRASmin(IDD), tRCD} = ^tRCD(IDD) ; CKE is HIGH,
mA
CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same
as IDD4W
Precharge power-down current ; All banks idle ; tCK = ^tCK(IDD) ; CKE is LOW ; Other control
IDD2P
mA
and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current;All banks idle; ^tCK = ^tCK(IDD);CKE is HIGH, CS is HIGH;
IDD2Q
mA
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current; All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS is HIGH; Other
IDD2N
mA
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current; All banks open; ^tCK = ^tCK(IDD); _{Fast PDN Exit MRS(12) = 0}
mA
IDD3P CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Slow PDN Exit MRS(12) = 1
mA
Active standby current; All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP}
IDD3N _{=tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus}
mA
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
IDD4W AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
mA
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4,
CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS
IDD4R
mA
is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as
IDD4W
Burst refresh current; ^tCK = ^tCK(IDD); Refresh command at every ^tRFC(IDD) interval; CKE is
IDD5B HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH- _mA
ING; Data bus inputs are SWITCHING
Rev. 0.7 / Oct. 2007
17