HY5PS12421BFP-E3 Datasheet, PDF (15/38 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
3.3.3 OCD default characteristics
Description
Output impedance
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
Parameter
Sout
Min
-
0
0
1.5
Nom
-
-
Max
-
1.5
4
5
Unit
ohms
ohms
ohms
V/ns
Notes
1
6
1,2,3
1,4,5,6,7,8
Note
1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/Ioh must be
less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink
dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC
to AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/variations and
represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the OCD impedance is 18 ohms
+/- 0.75 ohms under nominal conditions.
Output Slew rate load:
VTT
25 ohms
Output
(Vout)
Reference
point
7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and
tQHS specification.
Rev. 0.7 / Oct. 2007
15