HC6856 Datasheet, PDF (7/12 Pages) Honeywell Solid State Electronics Center – 32K x 8 STATIC RAM

HC6856
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
Parameter
Typical (2)
Worst Case (3)
SER <1E-9 (4)
SER <1E-10
Min Max
Min Max
Units
TAVAVW Write Cycle Time (5)
30
TWLWH Write Enable Write Pulse Width
25
TSLWH Chip Select to End of Write Time
25
TDVWH Data Valid to End of Write Time
20
TAVWH Address Valid to End of Write Time
25
TWHDX Data Hold Time after End of Write Time
0
TAVWL Address Valid Setup to Start of Write Time
0
TWHAX Address Valid Hold after End of Write Time
0
TWLQZ Write Enable to Output Disable Time
5
TWHQX Write Disable to Output Enable Time
15
TWHWL Write Disable to Write Enable Pulse Width
4
TEHWH Chip Enable to End of Write Time
25
40
60
ns
35
55
ns
35
55
ns
30
50
ns
35
55
ns
0
0
ns
0
0
ns
0
0
ns
0
10
0
10
ns
5
5
ns
5
5
ns
35
55
ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading0 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) SER ≤1E-10 u/b-d from -55 to 80°.
(5) TAVAVW= TWLWH + TWHWL
TAVAVW
ADDRESS
NWE
TAVWL
TWHWL
DATA OUT
HIGH
IMPEDANCE
TWLQZ
TAVWH
TWLWH
TDVWH
TWHAX
TWHQX
TWHDX
DATA IN
DATA VALID
NCS
CE
TSLWH
TEHWH
7