HC6856 Datasheet, PDF (6/12 Pages) Honeywell Solid State Electronics Center – 32K x 8 STATIC RAM

HC6856
READ CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
Parameter
Typical
(2)
Worst Case (3)
-55 to 125°C
Min Max
Units
TAVAVR Address Read Cycle Time
18
40
ns
TAVQV Address Access Time
18
40
ns
TAXQX Address Change to Output Invalid Time
15
5
ns
TSLQV Chip Select Access Time
20
40
ns
TSLQX Chip Select Output Enable Time
20
16
ns
TSHQZ Chip Select Output Disable Time
6
10
ns
TEHQV Chip Enable Access Time
20
40
ns
TEHQX Chip Enable Output Enable Time
20
16
ns
TELQZ Chip Enable Output Disable Time
6
10
ns
TGLQV Output Enable Access Time
4
10
ns
TGLQX Output Enable Output Enable Time
3
0
ns
TGHQZ Output Enable Output Disable Time
4
10
ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C_L >50 pF, or equivalent capacitive
output loading C_L=5 pF for TSHQZ, TELQZ TGHQZ. For C_L >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25°C.
ADDRESS
NCS
DATA OUT
TAVAVR
TAVQV
TSLQV
TSLQX
HIGH
IMPEDANCE
CE
NOE
(NWE = high)
TEHQX
TEHQV
TGLQX
TGLQV
TAXQX
DATA VALID
6
TSHQZ
TELQZ
TGHQZ