HI-6130_16 Datasheet, PDF (220/296 Pages) Holt Integrated Circuits – 3.3V BC / MT / RT Multi-Terminal Device

HI-6130, HI-6131
EEPROM programming is locked out at step 4 for the following conditions:
• ACTIVE output pin assertion occurs after MR master reset.
• RT1STEX bit 4, RT2STEX bit 5 or MTENA bit 8 is set in Master Configuration Reg 0x0000.
4. The host writes a 2-part “unlock code” to RAM address 0x004E. The unlock code value selectively enables any
combination of terminal devices (BC, MT, RT1, RT2) to automatically start execution, after subsequent auto-initial-
ization sequences are performed. Programmed here, the same combination of terminal devices is simultaneously
enabled after every initialization. Unlock words are encoded as shown in Table 18.
Table 18.  Terminal Unlock Word Encoding
Word 1
0xA00A
0xA03A
0xA0CA
0xA0FA
0xA30A
0xA33A
0xA3CA
0xA3FA
0xAC0A
0xAC3A
0xACCA
0xACFA
0xAF0A
0xAF3A
0xAFCA
0xAFFA
Word 2
0x5FF5
0x5FC5
0x5F35
0x5F05
0x5CF5
0x5CC5
0x5C35
0x5C05
0x53F5
0x53C5
0x5335
0x5305
0x50F5
0x50C5
0x5035
0x5005
Initialize RT1 ²
No auto init. ¹
X
X
Initialize RT2 ³
No auto init.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Initialize MT ⁴
No auto init.
X
X
X
X
X
X
X
X
Initialize BC ⁵
No auto init.
X
X
X
X
X
X
X
X
Note 1: Default. No terminal devices (BC, MT, RT1, RT2) are started. The host must write Master Configuration
Register 0x0000 to start terminals.
Note 2: The RT1ENA register bit 6 in register 0x0000 must be set before step 4. During auto-initialization events,
the RT1ENA and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization,
RT1STEX bit 4 is automatically set in Master Configuration. Register 0x0000, starting Remote Terminal RT1 execution.
Note 3: The RT2ENA register bit 7 in register 0x0000 must be set before step 4. During auto-initialization events,
the RT2ENA and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization,
RT2STEX bit 5 is automatically set in Master Configuration Register 0x0000, starting Remote Terminal RT2 execution.
Note 4: The MTENA register bit 8 in register 0x0000 must be set before step 4. During auto-initialization events, the
MTRUN and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization, the
SMT or IMT MTENA bit is automatically set in Master Configuration Register 0x0000, starting Bus Monitor execution.
Note 5: The BCENA register bit 12 in register 0x0000 must be set before step 4. During auto-initialization events,
the BCENA and AUTOEN input pins must be logic 1 before rising edge of MR master reset. After auto-initialization,
BCSTRT bit 13 is automatically pulsed in Master Configuration Register 0x0000, starting Bus Controller execution.
HOLT INTEGRATED CIRCUITS
220