HI-6130_16 Datasheet, PDF (177/296 Pages) Holt Integrated Circuits – 3.3V BC / MT / RT Multi-Terminal Device

HI-6130, HI-6131
Bit No. Mnemonic R/W Reset Function
Ping-Pong, Circular Buffer Mode 2 or Circular Buffer Mode 1 Enable.
The PPEN, CIR2EN and CIR1EN bits are initialized by the host to select buffer
mode. The table below summarizes how buffer mode selection is encoded.
In the case of ping-pong, the host initializes the PPEN bit to logic one after
reset to enable ping-pong buffering for this subaddress. The host asserts
STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the
2 PPEN
R/W
0
STOPP bit asks the device to re-enable ping-pong. The device confirms ping-
pong enable or disable state changes by writing the PPON bit. PPEN bit 2
1 CIR2EN R/W 0 _{should only be initialized or otherwise written when the applicable RT1ENA or}
0 CIR1EN R/W 0 ^{RT2ENA input pin is asserted, AND the corresponding RT1ENA or RT2ENA bit}
is also set in the Master Configuration Register 0x0000.
PPEN
CIR2EN
CIR1EN
Buffer Mode
1
Don’t Care
Don’t Care
Ping-Pong
0
1
Don’t Care
Circular Mode 2
0
0
1
Circular Mode 1
0
0
0
Indexed Single
Buffer
19.4.2. Transmit Subaddress Control Word
Transmit Subaddress Control Words apply when a valid command word T/R bit equals one (transmit) and the subaddress
field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response and
interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution begins. If
using ping-pong data buffers, Control Words should only be written when the applicable RT1ENA or RT2ENA input pin
is asserted AND the corresponding RT1ENA or RT2ENA bit is also set in the Master Configuration Register 0x0000.
Failure to meet this requirement prevents automatic assertion of PPON bit 8 when PPEN bit 2 is set, and successive
messages will repeatedly use the same buffer. Bits 8-11 cannot be written by the host; these bits are updated by the
device during terminal execution, that is, when the “Master Configuration Register (0x0000)” RT1STEX or RT2STEX
bits equal 1. The host can write bits 0-2 and 4-7 only when RT1STEX or RT2STEX equals zero; bits 3,12 and 14-15
can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the
DBAC, DPB and BCAST bits. Following any host read cycle to the Control Word address, the DBAC bit is reset.
MKBUSY
H H X H D1 D D D H H H H H H H H
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB
H Bit maintained by host
D Bit maintained by device
D1 Bit set by device, reset by host read cycle
X Bit is not used, may be logic 0 or 1
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
HOLT INTEGRATED CIRCUITS
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