HI-6130_16 Datasheet, PDF (160/296 Pages) Holt Integrated Circuits – 3.3V BC / MT / RT Multi-Terminal Device

HI-6130, HI-6131
18.14. RT1 and RT2 Remote Terminal Interrupt Registers and Their Use
Section 9.4 on page 37 through Section 9.6 describe how the host uses three Hardware Interrupt registers, the Interrupt
Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. When RT1/RT2 is enabled, three
additional registers are dedicated to the RT1/RT2 interrupts. Comparable to the Hardware Interrupt register triplet,
RT1/RT2 has
• A RT1/RT2 Interrupt Enable Register to enable and disable interrupts
• A RT1/RT2 Pending Interrupt Register to capture the occurrence of enabled interrupts
• A RT1/RT2 Interrupt Output Enable Register to enable IRQ output to host, for pending enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt
condition is enabled. Numerous interrupt options are available for RT1/RT2. At initialization, bits are set in the RT1/RT2
Interrupt Enable register to identify the interrupt-causing events for RT1/RT2 which are heeded by the HI-613x. Most
RT1/RT2 applications only use a subset of available RT1/RT2 interrupt options. Interrupt-causing events are ignored
when their corresponding bits are reset in the RT1/RT2 Interrupt Enable Register. Setting an Interrupt Enable register
bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero.
Whenever a RT1/RT2 interrupt event occurs (and the corresponding bit is already set in the RT1/RT2 Interrupt Enable
Register), these actions occur:
• The Interrupt Log Buffer is updated.
• A bit corresponding to the interrupt type is set in the RT1/RT2 Pending Interrupt Register. The type bit is logically-
ORed with the preexisting register value, retaining bits for prior, unserviced RT1/RT2 interrupts.
• RT Interrupt Pending (RTIP) bit 1 shared by RT1 and RT2 is set in the Hardware Pending Interrupt Register. The
RTIP bit is logically-ORed with the preexisting register value, retaining bits for unserviced hardware interrupts
and the preexisting status of the BCIP and MTIP (Bus Controller and MT) interrupt pending bits.
• If the matching bit is already set in the RT1/RT2 Interrupt Output Enable Register, an IRQ output occurs.
If the matching bit in the RT1/RT2 Interrupt Output Enable Register was not already set (i.e., low priority polled
interrupt), the host can poll the RT1/RT2 Pending Interrupt Register to detect the occurrence of RT1/RT2 interrupts,
indicated by non-zero value. Reading the RT1/RT2 Pending Interrupt Register automatically clears it to 0x0000.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four
Interrupt Output Enable registers (hardware, BC, RT and SMT or IMT). Multiple interrupt-causing events can occur
simultaneously, so single or simultaneous interrupt events can assert the IRQ host interrupt output.
When the host receives an IRQ signal from the device, it identifies the event(s) that triggered the interrupt. Section
9.4 describes two methods for identifying the interrupt source(s). One scheme uses the three low order bits in the
Hardware Pending Interrupt Register to indicate when BC, RT, SMT and/or IMT interrupts occur. When RT Interrupt
Pending (RTIP) bit 1 shared by RT1 and RT2 is set in the Hardware Pending Interrupt Register, the RT1/RT2 Pending
Interrupt Register contains a nonzero value and may be read next to identify the specific RT1/RT2 interrupt event(s).
Or, the host can directly interrogate the Interrupt Count & Log Address Register, followed by the Interrupt Log Buffer.
Data sheet section 9.4 has a detailed description.
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