HB288064MM1 Datasheet, PDF (74/79 Pages) Hitachi Semiconductor – MultiMediaCard 64 MByte

HB288064MM1
Clock
Input
t_WH
t_IH
Valid data
Output
t_OH
t_PP
t_WL
t_THL
t_TLH
Valid data
t_ISU
Valid data
t_OSU
V_IH
V_IL
V_IH
V_IL
V_OH
V_OL
: Invalid
Timing Diagram of Data Input and Output
The access time (t_AT) is divided into two parts:
• T_SAD: The synchronous access time. This time defines the time of the maximum number of cycles
which are required to access a byte of the memory field.
• T_AAD: The asynchronous access time to read a byte out of the memory field.
The synchronous part of the access time is sum of the command frame length and some additional internal
cycles (N_SAD = 16 cycles). At 20 MHz one cycle is 50 ns (1/f_CLK), multiplied with N_SAD the resulting frame
time is T_SAD = 0.8 µs. The asynchronous access delay of the HB288064MM1 is T_AAD = 300 µs maximum.
The resulting memory access time t_AT is the sum of both parts:
t_AT = T_AAD + T_SAD
with
T_SAD = N_SAD/f_CLK
T_SAD
t_AT
T_AAD
CMD
command frame
response frame
DAT
data
Access Time
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