HB288064MM1 Datasheet, PDF (45/79 Pages) Hitachi Semiconductor – MultiMediaCard 64 MByte

HB288064MM1
The host command and the card response are clocked out with the rising edge of the host clock. The delay
between host command and card response is N_CR clock cycles. The following timing diagram is relevant
for host command CMD3:
CMD
Host command
N_CR cycles
S T content CRC E Z * * * * * * Z S T
Host active
Response
content CRC E Z Z Z
Card active
Command Response Timing (Identification Mode)
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:
CMD
Host command
N_CR cycles
S T content CRC E Z Z P * * * P S T
Response
content CRC E Z Z Z
Host active
Card active
Command Response Timing (Data Transfer Mode)
• Card identification and card operation conditions timing
The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-
drain mode. The card response to the host command starts after exactly N_ID clock cycles.
CMD
Host command
N_ID cycles
S T content CRC E Z * * * Z S T
Host active
CID or OCR
content
Card active
ZZZ
Identification Timing (Card Identification Mode)
• Last card response - next host command timing
After receiving the last card response, the host can start the next command transmission after at least N_RC
clock cycles. This timing is relevant for any host command.
Response
N_RC cycles
Host command
CMD S T content CRC E Z * * * * * * Z S T content CRC E
Card active
Host active
Timing Response End to Next CMD Start (Data Transfer Mode)
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