2SK1297 Datasheet, PDF (4/7 Pages) Hitachi Semiconductor – Silicon N-Channel MOS FET

2SK1297
Power vs. Temperature Derating
120
80
40
0
50
100
150
Case Temperature T_C (°C)
Static Drain to Source on State
Resistance vs. Temperature
0.05
Pulse Test
0.04
0.03
I_D = 50 A
10 A, 20 A
V_GS = 4 V
0.02
0.01
V_GS = 10 V
50 A
10 A, 20 A
0
–40
0
40
80 120 160
Case Temperature T_C (°C)
Body to Drain Diode Reverse
Recovery Time
500
200
100
50
20
di/dt = 50 A/µs, Ta = 25°C
10
V_GS = 0
Pulse Test
5
0.5 1.0 2
5 10 20 50
Reverse Drain Current I_DR (A)
Maximum Safe Operation Area
500
200
100
50
20
10
5 _{Operation in this area}
is limited by R_{DS (on)}
2
Ta = 25°C
1.0
0.5
0.1 0.3 1.0 3
10 30 100
Drain to Source Voltage V_DS (V)
Forward Transfer Admittance
vs. Drain Current
50
20
–25°C
T_C = 25°C
10
75°C
5
2
V_DS = 10 V
1.0
Pulse Test
0.5 1.0 2
5 10 20 50
Drain Current I_D (A)
10000
Typical Capacitance vs.
Drain to Source Voltage
Ciss
V_GS = 0
f = 1 MHz
1000
Coss
Crss
100
10
0
10 20 30 40 50
Drain to Source Voltage V_DS (V)
4