HAT1043M Datasheet, PDF (2/9 Pages) Hitachi Semiconductor – Silicon P Channel Power MOS FET Power Switching

HAT1043M
Absolute Maximum Ratings (Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
V_DSS
–20
V
Gate to source voltage
V_GSS
±12
V
Drain current
I_D
–4.4
A
Drain peak current
I Note 1
D(pulse)
–17.6
A
Body-drain diode reverse drain current
I Note 2
DR
–4.4
A
Channel dissipation
Pch Note 2
(pulse)
2.0
W
Pch Note 3
(continuous)
1.05
W
Channel temperature
Tch
150
°C
Storage temperature
Tstg
–55 to +150
°C
Note:
1. PW ≤ 10 µs, duty cycle ≤ 1%
2. When using the alumina ceramic board (50 x 50 x 0.7 mm), PW ≤ 5 s, Ta = 25°C
3. When using the alumina ceramic board (50 x 50 x 0.7 mm), Ta = 25°C
Electrical Characteristics (Ta = 25°C)
Item
Symbol Min
Drain to source breakdown voltage V_(BR)DSS
Gate to source leak current
I _GSS
Zero gate voltege drain current
I _DSS
Gate to source cutoff voltage
V_GS(off)
Static drain to source on state
R_DS(on)
resistance
–20
—
—
–0.4
—
—
Forward transfer admittance
Input capacitance
|y_fs|
4
Ciss —
Output capacitance
Coss —
Reverse transfer capacitance
Crss —
Total Gate charge
Qg
—
Gate to Source charge
Qgs —
Gate to Drain charge
Qgd —
Turn-on delay time
t _d(on)
—
Rise time
t_r
—
Turn-off delay time
t _d(off)
—
Fall time
t_f
—
Body–drain diode forward voltage V_DF
—
Body–drain diode reverse
recovery time
t _rr
—
Note: 1. Pulse test
Typ Max Unit
—
—
V
—
±0.1 µA
—
–1
µA
—
–1.4 V
55
65
mΩ
85
110 mΩ
7
—
S
750 —
pF
310 —
pF
220 —
pF
11
—
nc
2
—
nc
3.5 —
nc
15
—
ns
100 —
ns
85
—
ns
100 —
ns
–0.95 –1.23 V
50
—
ns
Test Conditions
I_D = –10 mA, V_GS = 0
V_GS = ±12 V, V_DS = 0
V_DS = –20 V, V_GS = 0
I_D = –1 mA, V_DS = –10 V
I_D = –3 A, V_GS = –4.5 V ^{Note 1}
I_D = –3 A, V_GS = –2.5 V ^{Note 1}
I_D = –3 A, V_DS = –10 V ^{Note 1}
V_DS = –10 V
V_GS = 0
f = 1 MHz
V_DD = –10 V
V_GS = –4.5 V
I_D= –4.4 A
V_GS = –4.5 V, I_D = –3 A
R_L = 3.3 Ω
I_F = –4.4 A, V_GS = 0
I_F = –4.4 A, V_GS = 0
diF/ dt = –20 A/ µs
2