HN27C4000G Datasheet, PDF (18/20 Pages) Hitachi Semiconductor – 524288-Word ®8-Bit/262144-Word X 16-Bit CMOS UV Erasable and Programmable ROM

HN27C4000G Series
AC Characteristics (V_CC = 6.25 V ± 0.25 V, V_PP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall times: ≤ 20 ns
• Reference levels for measuring timings: Inputs; 0.8 V, 2.0 V
Outputs; 0.8 V, 2.0 V
Item
Symbol
Min
Typ
Max Unit Test conditions
Address setup time
OE setup time
t_AS
t_OES
2
—
—
µs
2
—
—
µs
Data setup time
t_DS
2
—
—
µs
Address hold time
t_AH
0
—
—
µs
Data hold time
OE high to output float delay
t_DH
t_DF*1
2
—
—
µs
0
—
130
ns
V_PP setup time
t_VPS
2
—
—
µs
V_CC setup time
CE initial programming
pulse width
t_VCS
t_PW
2
—
—
µs
47.5 50.0 52.5 µs
CE setup time
Data valid from OE
CE pulse width during data latch
OE = V_H setup time
OE = V_H hold time
t_CES
t_OE
t_LW
t_OHS
t_OHH
2
—
—
µs
0
—
150
ns
1
—
—
µs
2
—
—
µs
2
—
—
µs
Page programming reset time ^*2
V_PP hold time ^*2
t_VLW
t_VRS
1
—
—
µs
1
—
—
µs
Notes: 1. t_DF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
2. Page program mode will be reset when V_PP is set to V_CC or less.
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