GS8161E18 Datasheet, PDF (8/36 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
GS8161E18/32/36D 165-Bump BGA Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
BA, BB, BC, BD
NC
CK
BW
GW
E1
E3
E2
G
ADV
ADSC, ADSP
ZZ
FT
LBO
TMS
TDI
TDO
TCK
MCL
V_DD
V_SS
V_DDQ
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
—
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
Clock Input Signal; active high
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active l0w
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect Low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 2.13 11/2004
8/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology