GS8161E18 Datasheet, PDF (29/36 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
V_IHJ3
2.0
V_DD3 +0.3
V
1
3.3 V Test Port Input Low Voltage
V_ILJ3
–0.3
0.8
V
1
2.5 V Test Port Input High Voltage
V_IHJ2
0.6 * V_DD2
V_DD2 +0.3
V
1
2.5 V Test Port Input Low Voltage
V_ILJ2
–0.3
0.3 * V_DD2
V
1
TMS, TCK and TDI Input Leakage Current
I_INHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I_INLJ
–1
100
uA
3
TDO Output Leakage Current
I_OLJ
–1
1
uA
4
Test Port Output High Voltage
V_OHJ
1.7
—
V 5, 6
Test Port Output Low Voltage
Test Port Output CMOS High
V_OLJ
—
0.4
V_OHJC V_DDQ – 100 mV
—
V 5, 7
V 5, 8
Test Port Output CMOS Low
V_OLJC
—
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V_DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DDQ supply.
6. I_OHJ = –4 mA
7. I_OLJ = + 4 mA
8. I_OHJC = –100 uA
9. I_OHJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
V_DD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V_DDQ/2
Output reference level
V_DDQ/2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Load
DQ
50Ω
30pF^*
V_DDQ/2
* Distributed Test Jig Capacitance
Rev: 2.13 11/2004
29/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology