GS8161E18 Datasheet, PDF (17/36 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
Undershoot Measurement and Timing
V_IH
V_SS
50%
V_SS – 2.0 V
50% tKC
Overshoot Measurement and Timing
V_DD + 2.0 V
50%
50% tKC
V_DD
V_IL
Capacitance
(T_A = 25^oC, f = 1 MHZ, V_DD = 2.5 V)
Parameter
Symbol
Input Capacitance
C_IN
Input/Output Capacitance
C_I/O
Note:
These parameters are sample tested.
Test conditions
V_IN = 0 V
V_OUT = 0 V
AC Test Conditions
Parameter
Conditions
Input high level
V_DD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V_DD/2
Output reference level
V_DDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Typ. Max. Unit
4
5
pF
6
7
pF
Output Load 1
DQ
50Ω
30pF^*
V_DDQ/2
* Distributed Test Jig Capacitance
Rev: 2.13 11/2004
17/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology