GS8161E18 Datasheet, PDF (10/36 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
Single/Dual Cycle Deselect Control
L or NC
ZZ
H
L
SCD
H or NC
Active
Standby, I_DD = I_SB
Dual Cycle Deselect
Single Cycle Deselect
FLXDrive Output Impedance Control
L
ZQ
H or NC
High Drive (Low Impedance)
Low Drive (High Impedance)
9th Bit Enable
L
Activate DQPx I/Os (x18/x36 mode)
PE
H or NC
Deactivate DQPx I/Os (x16/x32 mode)
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and
the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.13 11/2004
10/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology