GS8171DW36AC Datasheet, PDF (7/33 Pages) GSI Technology – 18Mb Σ1x1Dp HSTL I/O Double Late Write SigmaRAM

CK
Address
ADV
/E1
ADV
/BA
/BB
DQA0-DQA8
DQB0-DQB8
CQ
GS8171DW36/72AC-350/333/300/250
Two Byte Write Control Example with Double Late Write SigmaRAM
W rite
W rite
W rite
No n -W rite
W rite
A
B
C
D
E
F
DA
DB
DE
DA
DC
Special Functions
Burst Cycles
Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read
or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to
simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the
internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in
a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
Rev: 1.04 4/2005
7/33
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology