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GS8171DW36AC Datasheet, PDF (27/33 Pages) GSI Technology – 18Mb Σ1x1Dp HSTL I/O Double Late Write SigmaRAM | |||
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GS8171DW36/72AC-350/333/300/250
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD â 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port AC Test Load
DQ
50â¦
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input High Voltage
VIHJ
0.6 * VDD
VDD +0.3
V
1
Test Port Input Low Voltage
VILJ
â0.3
0.3 * VDD
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
â300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
â1
100
uA
3
TDO Output Leakage Current
IOLJ
â1
1
uA
4
Test Port Output High Voltage
VOHJ
1.7
â
V 5, 6
Test Port Output Low Voltage
Test Port Output CMOS High
VOLJ
â
0.4
VOHJC VDDQ â 100 mV
â
V 5, 7
V 5, 8
Test Port Output CMOS Low
VOLJC
â
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be â2 V > Vi < VDDn +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ⤠VIN ⤠VDDn
3. 0 V ⤠VIN ⤠VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = â4 mA
7. IOLJ = + 4 mA
8. IOHJC = â100 uA
9. IOHJC = +100 uA
Rev: 1.04 4/2005
27/33
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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