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GS8171DW36AC Datasheet, PDF (16/33 Pages) GSI Technology – 18Mb Σ1x1Dp HSTL I/O Double Late Write SigmaRAM
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GS8171DW36/72AC-350/333/300/250
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
DC Input Logic High
VIH (dc)
VREF + 200
DC Input Logic Low
VIL (dc)
VREF - 200
DC Clock Input Differential Voltage
VDIF (dc)
400
VREF DC Voltage
VREF (dc)
VDDQ / 2 - 0.1
VDDQ / 2 + 0.1
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. SRAM performance is a function of clock input differential voltage (VDIF).
3. To guarantee AC characteristics, VIH,VIL,Trise and Tfall of inputs and clocks must be within 10% of each other.
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8V and 1.5V I/O drivers.
5. See AC Input Definition drawing below.
Units
mV
mV
mV
V
Notes
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units Notes
AC Input Logic High
VIH (ac)
VREF + 400
mV
3,4
AC Input Logic Low
VIL (ac)
VREF - 400
mV
3,4
AC Clock Input Differential Voltage
VDIF (ac)
800
mV
2,3
VREF Peak to Peak AC Voltage
VREF (ac)
5% VREF (DC)
mV
1
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. SRAM performance is a function of clock input differential voltage (VREF). The RAM can be operated with a single ended clocking with
either CK or CK tied to VREF.
3. To guarantee AC characteristics, VIH,VIL,Trise and Tfall of inputs and clocks must be within 10% of each other.
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8V and 1.5V I/O drivers.
5. See AC Input Definition drawing below.
HSTL I/O AC Input Definitions
VIH (ac)
VREF
VIL (ac)
VDIF
Rev: 1.04 4/2005
16/33
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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