GS8171DW36AC Datasheet, PDF (4/33 Pages) GSI Technology – 18Mb Σ1x1Dp HSTL I/O Double Late Write SigmaRAM

GS8171DW36/72AC-350/333/300/250
Pin Description Table
Symbol
A
ADV
Bx
W
E1
E2 & E3
EP2 & EP3
CK
CK
CQ, CQ
DQ
MCH
MCL
ZQ
TCK
TDI
TDO
TMS
NC
V_DD
V_DDQ
V_REF
V_SS
Description
Address
Advance
Byte Write Enable
Write Enable
Chip Enable
Chip Enable
Chip Enable Program Pin
Clock
Clock
Echo Clock
Data I/O
Must Connect High
Must Connect Low
Output Impedance Control
Test Clock
Test Data In
Test Data Out
Test Mode Select
No Connect
Core Power Supply
Output Driver Power Supply
Input Buffer Reference Voltage
Ground
Type
Input
Input
Input
Input
Input
Input
Mode Input
Input
Input
Output
Input/Output
Input
Input
Analog Input
Input
Input
Output
Input
—
Input
Input
Input
Input
Comments
—
Active High
Active Low
Active Low
Active Low
Programmable Active High or Low
To be tied directly to V_DD, V_DDQ or V_SS
Active High
Active Low
HSTL I/O Versions Only
Three State - Deselect via E2 or E3 False
Three State
Active High
To be tied directly to V_DD or V_DDQ
Active Low
To be tied directly to V_SS
To be tied to V_SS via RQ
Active High
—
—
—
Not connected to die or any other pin
1.8 V Nominal
1.5 V Nominal
HSTL I/O Versions Only
—
Operation Control
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of
the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 1.04 4/2005
4/33
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology