GS81314LT19 Datasheet, PDF (23/42 Pages) GSI Technology – 144Mb SigmaDDR-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LT19/37GK-933/800
NOPr and NOPw Requirements
The number of NOPw and NOPr needed during Write -> Read transitions, and the number of NOPr and NOPw needed during Read
-> Write transitions, are as follows:
Write -> Read Transition
Read -> Write Transition
NOPw (after Write)
min
typ
0
0
NOPr (before Read)
min
typ
0
0
NOPr (after Read)
min
typ
4
5~7
NOPw (before Write)
min
typ
3
4~6
Notes:
1. Min NOPw after Write (0) ensures that the SRAM disables DQ ODT 2.5 cycles after it latches the last piece of write data. Typ
NOPw is the same as Min NOPw because it is sufficient to ensure that the controller stops driving the last piece of write data
before SRAM DQ ODT disable reaches it (as the result of a subsequent NOPr or Read), regardless of SRAM tKQ, prop delay
between SRAM and controller, and operating frequency.
2. Min NOPr before Read (0) ensures that the SRAM drives Low 3 cycles before it begins driving the first piece of read data. Typ
NOPr is the same as Min NOPr because it is sufficient to ensure that the controller enables DQ ODT after SRAM Low drive
reaches it (and before the SRAM drives the first piece of read data), regardless of SRAM tKQ, prop delay between SRAM and
controller, and operating frequency.
3. Min NOPr after Read (4) ensures that the SRAM drives Low for 1 cycle after it stops driving the last piece of read data and before
it enables DQ ODT (as the result of a subsequent NOPw). Typ NOPr is greater than Min NOPr in order to ensure that the controller
disables DQ ODT after SRAM Low drive reaches is (and before the SRAM enables DQ ODT), accounting for SRAM tKQ, prop
delay between SRAM and controller, and operating frequency.
4. Min NOPw before Write (3) ensures that the SRAM enables DQ ODT 1 cycle before it latches the first piece of write data. Typ
NOPw is greater than Min NOPw in order to ensure that the controller begins driving the first piece of write data after SRAM
DQ ODT enable reaches it, accounting for SRAM tKQ, prop delay between SRAM and controller, and operating frequency.
DQ ODT Control Timing Diagram
Write1 Read1 NOPr1 NOPr2 NOPr3 NOPr4 NOPr5 NOPr6 NOPw1 NOPw2 NOPw3 NOPw4 NOPw5 Write2
CK, KD
SA A1 A2
A3
A4
LD
R/W
DQ D11 D12
t_KHDQT
t_KHQV
Q21 Q22
t_KHDQT
D31 D32
CQ
Note: In the diagram above, the controller is disabling its DQ ODT except from the beginning of NOPr5 to the beginning of NOPw3.
And while it is disabling its DQ ODT, the controller is driving DQ Low when it isn’t driving write data. Whereas, the SRAM is
enabling its DQ ODT except from the beginning of NOPr2 to the beginning of NOPw3. And while it is disabling its DQ ODT, the
SRAM is driving DQ Low when it isn’t driving read data.
Rev: 1.02 3/2016
23/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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