GS81314LT19 Datasheet, PDF (20/42 Pages) GSI Technology – 144Mb SigmaDDR-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LT19/37GK-933/800
State Truth Table
RST MRW LBKE LD R/W SA DQ (D)
1
X
X
X
X
X
X
0
1
X
0
X
V
X
0
0
1
X
X
X
X
0
1
X
1
See Clock Truth Table
0
0
0
X
Note: 1 = High; 0 = Low; V = Valid; X = don’t care.
SRAM State
Reset
Register Write Mode
Loopback Mode
Memory Mode
(Read, Write, NOP)
DQ (Q)
NOP State
Undefined
Loopback
See Clock Truth
Table
Clock Truth Table
SA MRW LD R/W
Current Operation
DQ (D)
DQ (Q)
CK
CK
CK
CK
(t_n)
(t_n)
(t_n)
(t_n)
(t_n)
KD
KD
CQ
CQ
(t_n)
(t_n+½)
(t_n+5)
(t_n+5½)
V
X
1
X
NOP
X
X
Hi-Z / other
V
0
0
0
Write
D1
D2
Hi-Z / other
V
0
0
1
Read
X
X
Q1
Q2
V
1
0
X
Register Write
X
X
Undefined
Notes:
1. 1 = High; 0 = Low; V = Valid; X = don’t care.
2. D1 and D2 indicate the first and second pieces of write data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of read data transferred during Read operations.
4. When DQ ODT is disabled, DQ pins are tri-stated for one cycle in response to NOP and Write commands, 5 cycles after the command is
sampled. See the DQ ODT Control section below for how the state of the DQ pins is controlled when DQ ODT is enabled.
Rev: 1.02 3/2016
20/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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