GS81314LT19 Datasheet, PDF (19/42 Pages) GSI Technology – 144Mb SigmaDDR-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LT19/37GK-933/800
Address Bus Utilization
The address bus is a non-multiplexed SDR bus. One memory address may be loaded per cycle - a read address at CK or a write
address at CK; consequently only one memory operation - a Read or a Write - may be initiated per clock cycle. The address bus is
also sampled at CK during a Register Write operation.
Address Bit Encoding
Command
Addr
Load
Device
21
20
19
18
17
16
15
14
SA Address Bits
13 12 11 10 9 8
7
6
5
4
3
2
1
0
Read
x36 NU
CK
x18
Address
Address
x36 NU
Write
CK
x18
Address
Address
Register
Write
CK
x36 NU X X X X X X X X X X
x18 X X X X X X X X X X X
Register Data
Register Data
Register # X
Register # X
Read Latency
Read Latency (i.e. the number of cycles from read command input to first read data output) is specified as follows:
Read Latency
5 cycles
Comment
First read data output 5 cycles after read command input
Note: The RLM register bit must be written to “0” in these devices prior to initiating Read operations, to set Read Latency = 5 cycles.
Write Latency
Write Latency (i.e. the number of cycles from write command input to first write data input) is specified as follows:
Write Latency
0 cycles
Comment
First write data input concurrent with write command input
Read / Write Coherency
These devices are fully coherent. That is, Read operations always return the most recently written data to a particular address, even
when a Read operation to a particular address occurs one cycle after a Write operation to the same address.
Rev: 1.02 3/2016
19/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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