GS81314LT19 Datasheet, PDF (22/42 Pages) GSI Technology – 144Mb SigmaDDR-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LT19/37GK-933/800
DQ Clock Truth Table
In the Truth Table below, gray shading indicates invalid operation sequences; they violate the Operation Sequence Rule.
MRW LD R/W
CK CK CK
(t_n)
(t_n)
(t_n)
Prior
Operation
(t_n-3)
Read
X
1
0 NOPw, NOPr, or Write
Register Write
Read
X
1
1 NOPw, NOPr, or Write
Register Write
Read
0
0
0
NOPw, NOPr, or Write
Read
0
0
1
NOPw, NOPr, or Write
0
NOPr or NOPw
1
0
1
X
Register Write
Note: 1 = High; 0 = Low; X = don’t care.
Current
Operation
(t_n)
NOPw
NOPw
NOPw
NOPr
NOPr
NOPr
Write
Write
Read
Read
Read
Read
Register Write
Future
Operation
(t_n+3)
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
X
DQ State
CK
(t_n+2)
Undefined
Terminated
Undefined
Read Data
0
Undefined
Undefined
Terminated
Read Data
0
Terminated
0
Undefined
CK
(t_n+5)
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Undefined
Read Data
Undefined
Read Data
Undefined
Rev: 1.02 3/2016
22/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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