GS8182T08 Datasheet, PDF (19/36 Pages) GSI Technology – 18Mb SigmaDDR-II™ Burst of 2 SRAM

GS8182T08/09/18/36BD-400/375/333/300/250/200/167
AC Electrical Characteristics
Parameter
Clock
-400
-375
-333
-300
-250
-200
-167
Symbol
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
K, K Clock Cycle Time
C, C Clock Cycle Time
t_KHKH
t_CHCH
2.5 8.4 2.67 8.4 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
tTKC Variable
t_KCVar
— 0.2 — 0.2 — 0.2 — 0.2 — 0.2 — 0.2 — 0.2 ns 6
K, K Clock High Pulse Width
C, C Clock High Pulse Width
t_KHKL
t_CHCL
1.0
— 1.13 — 1.2
— 1.32 —
1.6 — 2.0
—
2.4
— ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
t_KLKH
t_CLCH
1.0
— 1.13 — 1.2
— 1.32 —
1.6 — 2.0
—
2.4
— ns
K to K High
C to C High
t_KHKH
t_CHCH
1.0
— 1.13 — 1.35 — 1.49 —
1.8
—
2.2
—
2.7
— ns
K to K High
C to C High
t_KHKH
t_CHCH
1.0
— 1.13 — 1.35 — 1.49 —
1.8
—
2.2
—
2.7
— ns
K, K Clock High to C, C Clock High t_KHCH
0 1.1 0 1.2 0 1.3 0 1.45 0 1.8 0
2.3 0 2.8 ns
DLL Lock Time
t_KCLock 1024
—
1024
—
1024
—
1024
—
1024
—
1024
—
1024
—
cy
cle
6
K Static to DLL reset
Output Times
t_KCReset
30
—
30
—
30
—
30
—
30
—
30
—
30
— ns
K, K Clock High to Data Output Valid ^tKHQV
C, C Clock High to Data Output Valid t_CHQV
— 0.45 — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 4
K, K Clock High to Data Output Hold ^tKHQX
C, C Clock High to Data Output Hold t_CHQX
–0.45 — –0.45 — –0.45 —
–0.45
— –0.45 — –0.45 —
–0.5
— ns 4
K, K Clock High to Echo Clock Valid ^tKHCQV
C, C Clock High to Echo Clock Valid t_CHCQV
— 0.45 — 0.45 — 0.45 —
0.45 — 0.45 — 0.45 —
0.5 ns
K, K Clock High to Echo Clock Hold ^tKHCQX
C, C Clock High to Echo Clock Hold t_CHCQX
–0.45
—
–0.45
—
–0.45
—
–0.45
— –0.45 — –0.45 —
–0.5
— ns
CQ, CQ High Output Valid
t_CQHQV — 0.25 — 0.25 — 0.25 — 0.27 — 0.30 — 0.35 — 0.40 ns 8
CQ, CQ High Output Hold
t_CQHQX –0.25 — –0.25 — –0.25 — –0.27 — –0.30 — –0.35 — –0.40 — ns 8
CQ Phase Distortion
t_CQHCQH
t_CQHCQH
0.9
—
1.0
— 1.10 — 1.24
— 1.55 — 1.95 — 2.45 — ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
t_KHQZ
t_CHQZ
— 0.45 — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 4
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
t_KHQX1
t_CHQX1
–0.45
—
–0.45
—
–0.45
—
–0.45
— –0.45 — –0.45 —
–0.5
— ns 4
Setup Times
Address Input Setup Time
t_AVKH
0.4 — 0.4 — 0.4 —
0.4
—
0.5 — 0.6 — 0.7 — ns 1
Control Input Setup Time (R/W, LD) t_IVKH
0.4 — 0.4 — 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns 2
Control Input Setup Time (BWX,
NWX)
t_IVKH
0.28 — 0.28 — 0.28 —
0.3
— 0.35 —
0.4
—
0.5
— ns 3
Data Input Setup Time
t_DVKH
0.28 — 0.28 — 0.28 —
0.3
— 0.35 —
0.4
—
0.5
— ns
Rev: 1.04c 11/2011
19/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology