GS8182T08 Datasheet, PDF (15/36 Pages) GSI Technology – 18Mb SigmaDDR-II™ Burst of 2 SRAM

GS8182T08/09/18/36BD-400/375/333/300/250/200/167
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Input Logic High
V_IH (dc)
V_REF + 0.10
V_DDQ + 0.3 V
V
1, 4
DC Input Logic Low
V_IL (dc)
–0.3 V
V_REF – 0.10
V
1, 3
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is V_REF ± 50 mV. The AC V_IH/V_IL levels are defined separately for measuring timing
parameters.
3. V_IL (Min) DC = –0.3 V, V_IL(Min) AC = –1.5 V (pulse width ≤ 3 ns).
4. V_IH (Max) DC = V_DDQ + 0.3 V, V_IH(Max) AC = V_DDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
AC Input Logic High
V_IH (ac)
V_REF + 0.20
—
V
AC Input Logic Low
V_IL (ac)
—
V_REF – 0.20
V
V_REF Peak-to-Peak AC Voltage
V_REF (ac)
—
5% V_REF (DC)
V
Notes:
1. The peak-to-peak AC component superimposed on V_REF may not exceed 5% of the DC component of V_REF.
2. To guarantee AC characteristics, V_IH,V_IL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Notes
2, 3
2, 3
1
Undershoot Measurement and Timing
V_IH
V_SS
50%
V_SS – 1.0 V
20% tKHKH
Capacitance
(T_A = 25^oC, f = 1 MHZ, V_DD = 3.3 V)
Parameter
Input Capacitance
Output Capacitance
Clock Capacitance
Note:
This parameter is sample tested.
Symbol
C_IN
C_OUT
C_CLK
Overshoot Measurement and Timing
V_DD + 1.0 V
50%
20% tKHKH
V_DD
V_IL
Test conditions
V_IN = 0 V
V_OUT = 0 V
—
Typ.
Max.
Unit
4
5
pF
6
7
pF
5
6
pF
Rev: 1.04c 11/2011
15/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology