GS8182T08 Datasheet, PDF (11/36 Pages) GSI Technology – 18Mb SigmaDDR-II™ Burst of 2 SRAM

GS8182T08/09/18/36BD-400/375/333/300/250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
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resistor, RQ,
desired RAM
to allow the SRAM to monitor and adjust its output driver impedance. The value
output impedance. The allowable range of RQ to guarantee impedance matching
of RQ must be
continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and tempera-
ture. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may
move the output driver impedance level one step at a time towards the optimum level.
Common I/O SigmaDDR-II B2 SRAM Truth Table
K_n
LD
R/W
↑
1
X
↑
0
0
↑
0
1
Note:
Q is controlled by K clocks if C clocks are not used.
DQ
A+0
A+1
Hi-Z
Hi-Z
D@K_n+1
Q@K_n+1
or
C_n+1
D@K_n+1
Q@K_n+2
or
C_n+2
Operation
Deselect
Write
Read
B2 Byte Write Clock Truth Table
BW
BW
Current Operation
K↑
(t_n+1)
T
K↑
(t_n+2)
T
K↑
(t_n)
Write
Dx stored if BWn = 0 in both data transfers
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
D
K↑
(t_n+1)
D1
D1
X
X
D
K↑
(t_n+2)
D2
X
D2
X
Rev: 1.04c 11/2011
11/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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