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GS82032AT Datasheet, PDF (17/22 Pages) GSI Technology – 64K x 32 2Mb Synchronous Burst SRAM
GS82032AT-180/166/150/133/100/66/4/5/6
Sleep Mode Timing
CK
ADSP
tKH
tKC
tKL
Setup
Hold
ADSC
ZZ
tZZR
tZZS
tZZH
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.12 10/2004
17/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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