GS82032AT Datasheet, PDF (11/22 Pages) GSI Technology – 64K x 32 2Mb Synchronous Burst SRAM

GS82032AT-180/166/150/133/100/66/4/5/6
Undershoot Measurement and Timing
V_IH
V_SS
50%
V_SS – 2.0 V
20% tKC
Overshoot Measurement and Timing
V_DD +- 2.0 V
50%
20% tKC
V_DD
V_IL
Capacitance
(T_A = 25°C, f = 1 MHZ, V_DD = 3.3 V)
Parameter
Control Input Capacitance
Input Capacitance
Output Capacitance
Note:
This parameter is sample tested.
Symbol
C_I
C_IN
C_OUT
Test conditions
V_DD = 3.3 V
V_IN = 0 V
V_OUT = 0 V
AC Test Conditions
Parameter
Conditions
Input high level
2.3 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
Output load
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t_LZ, t_HZ, t_OLZ and t_OHZ
4. Device is deselected as defined by the Truth Table.
Typ. Max. Unit
3
4
pF
4
5
pF
6
7
pF
Output Load 1
DQ
Output Load 2
2.5 V
50Ω
30pF^*
DQ
225Ω
VT = 1.25 V
* Distributed Test Jig Capacitance
5pF^{* 225Ω}
Rev: 1.12 10/2004
11/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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