GS8160EV18AT Datasheet, PDF (1/24 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

100-Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
1M x 18, 512K x 32, 512K x 36 ^{350 MHz–150 MHz}
18Mb Sync Burst SRAMs
1.8 V V_DD
1.8 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS8160EV18/32/36AT is an 18,874,368-bit (16,777,216-
bit for x32 version) high performance synchronous SRAM
with a 2-bit burst address counter. Although of a type
originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
DCD Pipelined Reads
The GS8160EV18/32/36AT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Controls
Sleep Mode
Addresses, data I/Os, chip enables (E1, E2, E3), address burst ^{Low power (Sleep mode) is attained through the assertion}
control inputs (ADSP, ADSC, ADV), and write control inputs ^{(High) of the ZZ signal, or by stopping the clock (CK).}
(Bx, BW, GW) are synchronous and are controlled by a
Memory data is retained during Sleep mode.
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
Core and Interface Voltages
The GS8160EV18/32/36AT operates on a 1.8 V power supply.
All input are 1.8 V compatible. Separate output power (V_DDQ)
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
Parameter Synopsis
-350 -333 -300 -250 -200 -150 Unit
Pipeline
3-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
1.8 2.0 2.2 2.3 2.7 3.3 ns
2.85 3.0 3.3 4.0 5.0 6.7 ns
395 370 335 280 230 185 mA
455 430 390 330 270 210 mA
Flow
Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
4.5 4.7 5.0 5.5 6.5 7.5 ns
4.5 4.7 5.0 5.5 6.5 7.5 ns
270 250 230 210 185 170 mA
305 285 270 240 205 190 mA
Rev: 1.00a 6/2003
1/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.