GS2962 Datasheet, PDF (47/82 Pages) Gennum Corporation – Integrated Narrow-Bandwidth PLL

4.8 Additional Processing Functions
The GS2962 contains a number of signal processing features. These features are only
enabled in SMPTE mode of operation (SMPTE_BYPASS = HIGH), and when I/O
processing is enabled (IOPROC_EN/DIS = HIGH).
Signal processing features include:
• TRS generation and insertion
• Line number calculation and insertion
• Line based CRC calculation and insertion
• Illegal code re-mapping
• SMPTE 352M payload identifier packet insertion
• ANC checksum calculation and correction
• EDH generation and insertion
• SMPTE 372M conversion
To enable these features in the GS2962, the SMPTE_BYPASS pin must be HIGH, the
IOPROC_EN/DIS pin must be HIGH and the individual feature must be enabled via bits
set in the IOPROC register of the host interface. By default, all of the processing features
are enabled, except for SMPTE 372M correction.
4.8.1 Video Format Detection
By using the timing parameters extracted from the received TRS signals, or the supplied
external timing signals, the GS2962 calculates the video format.
The total samples per line, active samples per line, total lines per field/frame, and active
lines per field/frame are measured and reported to the user via the four
RASET_STRUC_X registers in the host interface.
These line and sample count registers are updated once per frame at the end of line 12.
The RASET_STRUC_X registers also contain two status bits: STD_LOCK and INT/PROG.
The STD_LOCK bit is set HIGH whenever the automatic video format detection circuit
has achieved full synchronization.
The INT/PROG bit is set LOW if the detected video standard is Progressive, and is set
HIGH if the detected video standard is Interlaced.
The Gennum video standard code (VD_STD), as used in the GS2972, GS1582 and
GS1572, is included in Table 4-5 for reference purposes.
NOTE: If proper SMPTE video is applied and then removed from the input, the device
does not flag that the H_LOCK, V_LOCK, VD_SDT etc. has changed (been lost). This is the
case for either TRS detect or HVF modes. This problem occurs only when the video data
is removed, but not the PCLK. Usually, when a video signal is removed, it includes the
clock, the video data, as well as the H, V, F as a whole. So the scenario is not likely to
occur, but the user should be aware of this issue.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
47 of 82