GS2962 Datasheet, PDF (11/82 Pages) Gennum Corporation – Integrated Narrow-Bandwidth PLL

Table 1-1: Pin Descriptions (Continued)
Pin
Number
E3, E4
Name
Timing
Type
RATE_SEL0,
RATE_SEL1
Input
Description
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Used to configure the operating data rate.
RATE_SEL0
0
RATE_SEL1
0
Data Rate
1.485 or 1.485/1.001Gb/s
0
1
2.97 or 2.97/1.001Gb/s
1
X
270Mb/s
E7
TDI
E8
TMS
E10
F1, F2, H1,
H2, J1, J2,
J3, K1, K2,
K3
CD_VDD
DIN[9:0]
F3
DETECT_TRS
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
Test data in.
This pin is used to shift JTAG test data into the device when the
JTAG/HOST pin is LOW.
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
Test mode start.
This pin is JTAG Test Mode Start, used to control the operation of
the JTAG test when the JTAG/HOST pin is LOW.
Input Power Power for the serial digital cable driver. Connect to 3.3V DC analog.
Input
PARALLEL DATA BUS.
Signal levels are LVCMOS / LVTTL compatible.
In 10-bit mode, these pins are not used.
20-bit mode
20BIT/10BIT = HIGH
Data Stream 2/Chroma data input in
SMPTE mode SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Not Used in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20BIT/10BIT = LOW
Not used.
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device extracts all internal timing
from the supplied H:V:F or CEA-861 timing signals, dependent on
the status of the TIM861 pin.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
11 of 82